Optimize the task schedule to improve the handling speed and real-time capability for ESP8266 based programmable controller

Optimize the ESP8266’s freertos task scheduling to improve the programmable controller’s web page download speed and ensure the controller’s processing real-time capability.

A few days ago, the communication performance of the controller was tested by…


This content originally appeared on DEV Community and was authored by zhuyue

Optimize the ESP8266's freertos task scheduling to improve the programmable controller's web page download speed and ensure the controller's processing real-time capability.

A few days ago, the communication performance of the controller was tested by downloading web pages in an automatic loop as a way of verifying that the problems of unpacking and sticking of TCP data streams had been solved.

I modified the PC tool to statistic the time for sending and receiving of individual data as well as the downloading of the entire web page;

The whole web page is split into 350 packets and sent to the controller, the length of each packet is 1024 Byte, the total time consumed is about 40 seconds, which takes about 30ms to write 1024byte data to the flash, and the total time consumed is about 10s, the speed of TCP communication is 95kbit/s in both directions, and the unidirectional sending and receiving of data can reach the 200kbit/s communication speed. speed; 

In order to further improve the communication speed and ensure the overall response in real time, I made the following improvements:
1) Modify the read/write program of flash, because when reading/writing spi flash through spi_flash_read and spi_flash_write functions, the flash address, data length and the memory for storing the data need to be aligned with 4 bytes, in order to solve the problem, I modify the read/write program to read/write flashf by 4 bytes one by one, which make spi read and write every 4 bytes of data need to write 4 bytes of 4 addresses, greatly reducing the speed of flash read and write, I modified the code to determine if the upper layer of the incoming address, length and memory are 4 bytes aligned, it is still directly call spi_flash_write or spi_flash_read read and write.

After testing, the time to write 512 bytes of data is reduced from 10ms to 3.8ms, and the time to read 512 bytes is reduced from 3ms to 0.5ms;.
2) Adjust the priority of the task that handles the controller's business logic, the code enables both preemptive scheduling as well as time-slice scheduling, according to the task scheduling strategy of freertos, the high priority task can preempt the low priority task, before the modification, the controller's business processing main task's priority is 1, and the lwip's task's priority is 8, the lwip's task will preempt the main task, making the The running time of the main task is too long, which affects the parsing and processing of received tcp packets and the generation of answer messages.

In order to ensure the real-time control logic, I adjusted the priority of the main task to the highest 11, and after running all the code of the control business, I called the vTaskDelay function to release the CPU time for other low-priority task scheduling.

Thus, the control logic code is strictly guaranteed to be scheduled at 10ms intervals.

After these two changes, the web page download time from 40s down to 28s, but I think there is still room for improvement, and I am going to further optimize the tcp/ip data sending.

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This content originally appeared on DEV Community and was authored by zhuyue


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